Amplifier circuit and method therefor

ABSTRACT

In one embodiment, an amplifier circuit is formed to minimize pop and click noise on the outputs of the amplifier circuit. The amplifier circuit is configured to place an output stage of the amplifier circuit in a high impedance state to minimize the pop and click noise. In another embodiment, the amplifier circuit is configured to couple the inputs of two amplifiers together to minimize the pop and click noise.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to electronics, and moreparticularly, to methods of forming semiconductor devices and structure.

In the past, the semiconductor industry utilized various methods andcircuits to form audio amplifiers. These audio amplifiers generallyreceived an input signal and differentially drove a speaker in order toform sound. Examples of such audio amplifiers were disclosed in U.S.Pat. No. 5,939,938 issued to Kalb et al. on Aug. 17, 1999 and in U.S.Pat. No. 6,346,854 issued to Christopher B. Heitoffl on Feb. 12, 2002.One problem with these prior audio amplifiers was turn-on and turn-offtransients that created noise during the turn-on and turn-off time. Theturn-on and turn-off transients produced noises generally referred to aspop or click noises which degraded the usability of the audio amplifier.

Accordingly, it is desirable to have an amplifier that reduces theturn-on and turn-off transients and the pop and click noise.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates an embodiment of a portion of a systemthat has an exemplary embodiment of an amplifier circuit in accordancewith the present invention;

FIG. 2 is a graph illustrating states of some of the signals formed bythe amplifier circuit of FIG. 1 in accordance with the presentinvention;

FIG. 3-FIG. 5 schematically illustrate different states of the amplifiercircuit of FIG. 1 in accordance with the present invention;

FIG. 6 schematically illustrates an alternate embodiment of portions ofthe amplifier circuit of FIG. 1 in accordance with the presentinvention;

FIG. 7 schematically illustrates another alternate embodiment ofportions of the amplifier circuit of FIG. 1 in accordance with thepresent invention;

FIG. 8 schematically illustrates an embodiment of a portion of anothersystem that uses the amplifier circuit of FIG. 1 in a differentconfiguration in accordance with the present invention; and

FIG. 9 schematically illustrates an embodiment of a portion of anothersystem that has an exemplary embodiment of another amplifier circuit inaccordance with the present invention;

FIG. 10 illustrates an enlarged plan view of a semiconductor device thatincludes the amplifier circuit of FIG. 1 in accordance with the presentinvention.

For simplicity and clarity of the illustration, elements in the figuresare not necessarily to scale, and the same reference numbers indifferent figures denote the same elements. Additionally, descriptionsand details of well-known steps and elements are omitted for simplicityof the description. As used herein current carrying electrode means anelement of a device that carries current through the device such as asource or a drain of an MOS transistor or an emitter or a collector of abipolar transistor or a cathode or anode of a diode, and a controlelectrode means an element of the device that controls current throughthe device such as a gate of an MOS transistor or a base of a bipolartransistor. Although the devices are explained herein as certainN-channel or P-Channel devices, a person of ordinary skill in the artwill appreciate that complementary devices are also possible inaccordance with the present invention. It will be appreciated by thoseskilled in the art that the words during, while, and when as used hereinare not exact terms that mean an action takes place instantly upon aninitiating action but that there may be some small but reasonable delay,such as a propagation delay, between the reaction that is initiated bythe initial action.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates an embodiment of a portion of anamplifier system 10 that uses an exemplary embodiment of an amplifiercircuit 25 to amplify signals received by circuit 25 and to drive a loadwith the amplified signals. Typically, circuit 25 receives audio signalsand drives an audio load such as an audio speaker 23. Amplifier circuit25 receives power, such as from a DC voltage source 21, between avoltage input 26 and a voltage return 27. Thus, circuit 25 operates froma single voltage power source. A bypass capacitor 20 generally isutilized to assist in forming a stable reference voltage for theoperation of circuit 25. In the exemplary embodiment illustrated in FIG.1, system 10 provides a differential input signal that is to beamplified as illustrated by differential signal sources 11 and 12.Sources 11 and 12 typically are audio signal sources. Blockingcapacitors 14 and 16 decouple DC voltages of respective sources 11 and12 from the inputs of circuit 25. Input resistors 15 and 17 areconnected between respective capacitors 14 and 16 and the inputs tocircuit 25.

Circuit 25 receives the input signals on signal inputs 33 and 34.Circuit 25 also includes a bypass input 29, a turn-on input 30, anddifferential outputs 31 and 32. Circuit 25 further includes a bypassbuffer 35, a first multi-stage amplifier 60, a second multi-stageamplifier 50, and a clock control circuit or control 47. Bypass buffer35 includes a reference voltage source formed as a resistor dividerusing resistors 36 and 38 that form a reference voltage at a node 37, anamplifier 40, an output resistor 41, a switch such as a switchtransistor 42, another switch such as a switch transistor 43, and aninverter 44. First multi-stage amplifier 60 includes a plurality ofamplifier stages connected together in series with feedback elements inorder to provide sufficient gain and drive to amplify the input signalsand drive the load of speaker 23. Amplifier 60 includes a firstamplifier 61, such as a trans-conductance amplifier, an output stageamplifier 62, such as a trans-conductance amplifier, and an outputresistor 66. An external resistor 18 is connected between output 32 andinput 34 and functions as a feedback resistor for amplifier 60.Amplifier 50 includes a first amplifier 51, such as a trans-conductanceamplifier, an output stage amplifier 52, such as a trans-conductanceamplifier, and a feedback resistor 57. Although amplifiers 50 and 60 areillustrated with two stages of amplifiers, 51 and 52 and 61 and 62,amplifiers 50 and 60 may include any number of intermediate amplifierstages in addition to amplifiers 51 and 52 and amplifiers 61 and 62.Output stage amplifiers 52 and 62 may have a variety of configurationsincluding a differential amplifier or a simple general gain stage.Additionally, output stage amplifiers 52 and 62 are each formed with anenable control input that is used to control the output transistors ofrespective amplifiers 52 and 62. When the enable control input isnegated, the output transistors of amplifiers 52 and 62 are disabledwhich places the output of amplifiers 52 and 62 in a high impedancestate so that amplifiers 52 and 62 do not drive outputs 31 and 32. Whenthe enable control signal is asserted, the output transistors ofamplifiers 52 and 62 are enabled so that amplifiers 52 and 62 driveoutputs 31 and 32 responsively to the signals on the inputs toamplifiers 52 and 62. Control 47 generates a plurality of controlsignals there used to control the startup sequence of circuit 25. Thecontrol signals form three operating states that are utilized tosequence the operation of some of the elements of circuit 25 in order tominimize pop and click noise on outputs 31 and 32. Control 47 generallyincludes a clock circuit that forms a timing reference signal anddigital logic that uses the timing reference signal to form the timeintervals of the different operating states. Circuit 25 also includesswitches, implemented as switch transistors 49, 55, 56, 64, and 65, thatalso assist in the start-up sequencing of circuit 25. Although notillustrated in the exemplary embodiment of FIG. 1, those skilled in theart will appreciate that most of the elements of circuit 25, such ascontrol 47 and amplifiers 50 and 60, are connected to receive powerbetween input 26 and return 27.

FIG. 2 is a graph having plots that illustrate some states of some ofthe signals formed by circuit 25. The abscissa indicates time and theordinate indicates increasing amplitude of the illustrated signal. Aplot 70 illustrates the turn-on input signal (ON) on input 30 of circuit25. Plots 71, 72, 73, and 74 illustrate respective control signals C1,C2, C3, and C4 that are formed on outputs of control 47. Thisdescription has references to FIG. 1 and FIG. 2. Prior to circuit 25receiving power from source 21 between input 26 and return 27, bypasscapacitor 20 is discharged and input capacitors 14 and 16 are alsodischarged. Circuit 25 is configured to form a plurality of operatingstates during a start-up sequence. These different operating states areformed to minimize the pop and click noise formed by speaker 23.

FIG. 3 schematically illustrates system 10 during a first operatingstate of circuit 25. In FIG. 3, transistors 42, 43, 49, 55, 56, 64, and65 are illustrated by switches that show the state (enabled or disabled)of the respective transistors responsively to the control signals ofcontrol 47. Referring to FIG. 2 and FIG. 3, at a time T0 source 21begins to apply power to circuit 25 and input 30 is driven high tosignal circuit 25 to turn-on and begin the startup sequence. Sincecapacitors 14, 16, and 20 are discharged, circuit 25 must charge thecapacitors and at the same time prevent forming output signals onoutputs 31 and 32 that would drive speaker 23. The low to hightransition of the ON signal causes control 47 to place signals C1, C2,C3, and C4 in a first state, as illustrated between T0 and a time T1 inFIG. 2, and cause control circuit 25 to operate in the first operatingstate. The high ON signal also enables buffer 40 to begin operating. Inthis first state, signals C1 and C2 are low, and signals C3 and C4 arehigh. The low C1 signal disables the output of amplifiers 52 and 62 andplaces the output of amplifiers 52 and 62 in a high impedance state sothat amplifiers 52 and 62 supply no current and do not drive to outputs31 and 32. Thus, outputs 31 and 32 are not driven and circuit 25 doesnot generate any noise through speaker 23. Amplifiers 52 and 62 areillustrated by dashed lines to represent that the outputs are in a highimpedance state and do not drive outputs 31 and 32. The low C2 signaldisables transistors 56 and 65. The high C3 signal enables transistors55 and 64 which connects the output of respective amplifiers 51 and 61to the respective inverting input of amplifiers 51 and 61. The high C4signal enables transistor 42 and disables transistor 43 which connectsamplifier 40 in a unity gain configuration. The high C4 signal alsoenables transistor 49 which connects the non-inverting input ofamplifier 51 to the non-inverting input of amplifier 61. Thus,amplifiers 51 and 61 are connected in a closed loop followerconfiguration. In this configuration, the output of amplifiers 51 and 61follows the voltage on input 29.

As the voltage from voltage source 21 increases, the divider ofresistors 36 and 38 forms an increasing voltage on node 37. Amplifier 40receives the voltage from node 37 and drives input 29 and capacitor 20.Amplifier 40 has a sufficient current drive capability to drivecapacitor 20 so that the voltage on input 29 increases at a rate that issufficient for the voltage at input 29 to reach the voltage of node 37and to settle within a fraction of the time interval between times T0and T1. Because of the follower configuration of amplifiers 51 and 61and because transistor 49 is enabled, capacitors 14 and 16 are alsocharged to the voltage that buffer 35 forms on input 29. Thus, all ofthe capacitors are charged to the same voltage over the same timeinterval. In the preferred embodiment, resistors 36 and 38 haveapproximately equal values, thus, the voltage on node 37 isapproximately one-half of the voltage provided by source 21.

In this configuration, the gain of any differential signal resultingfrom an imbalance in the voltages on the outputs of amplifiers 51 and 61to the signal formed across speaker 23 is set by the resistance ofspeaker 23 and resistors 66 and 18 as shown by the equation below:

V31−V32=(V51−V61)(R23/(R66+2R18))

where;

-   -   V51−V61=the differential voltage between the output of amplifier        51 and the output of amplifier 61;    -   V31−V32=the differential voltage between outputs 31 and 32;    -   R23=the resistance of speaker 23;    -   R18=the resistance of resistor 18; and    -   R66=the resistance of resistor 66.        Those skilled in the art will appreciate that this gain shown        above is the gain between the differential input signal from        inputs 33 and 34 to the differential output signal between        outputs 31 and 32.

In one example embodiment, resistor 66 is twenty thousand (20,000) ohms,resistor 18 is ten thousand (10,000) ohms, and the resistance of speaker23 is about eight (8) ohms. Thus, the equation reduces to:

V31−V32=(V51−V61)(8/(20000+20000))=(V51−V61)/5000.

Thus, even if there were a differential signal between the outputs ofamplifiers 51 and 61 the gain is so small, that this signal would not beheard.

Control 47 maintains circuit 25 in this first operating state for timeinterval that is sufficient for the voltage on input 29 to reach thedesired operating value and for circuit 25 to charge capacitors 14, 16,and 20 to the voltage on node 37. Control 47 determines the timeinterval as function of time and not a function of any voltage values.Control 47 subsequently changes the state of the control signals toplace circuit 25 in the second operating state of the start-up sequence.

FIG. 4 schematically illustrates system 10 during the second operatingstate of the startup sequence of circuit 25. In FIG. 4, transistors 42,43, 49, 55, 56, 64, and 65 are illustrated by switches that show thestate (enabled or disabled) of the respective transistors responsivelyto the control signals of control 47. Referring to FIG. 2 and FIG. 4, ata time T1 control 47 forces the C1, C2, and C4 control signals high andthe C3 control signal low in order to place circuit 25 in the secondoperating state. The high C1 control signal enables the outputs ofamplifiers 52 and 62 and removes the outputs from the high impedancestate so that amplifiers 52 and 62 may drive respective outputs 31 and32. The high C2 control signal enables transistors 56 and 65 while thelow C3 control signal disables transistors 55 and 64. The high C4control signal maintains transistors 42 and 49 in the enabled conditionand transistor 43 in the disabled state. This places amplifiers 50 and60 in a unity gain configuration. Also, buffer 35 continues to form thevoltage on input 29 to maintain capacitors 14, 16, and 20 at the voltageof node 37. Because capacitors 14, 16, and 20 are all held atsubstantially the same voltage by buffer 35 and transistors 49 and 65,the output of amplifiers 50 and 60 are substantially equal and nocurrent is driven through speaker 23. Control 47 maintains circuit 25 inthis second operating state for a time interval that is sufficient toenable the outputs of amplifiers 52 and 62 and ensure that amplifiers 52and 62 are able to drive speaker 23. In this configuration of the secondoperating state, the gain of any differential signal through the pathfrom inputs 33 or 34 to outputs 31 and 32 is close to unity. Since thevoltage difference between the inputs of amplifiers 50 and 60 is nearlyzero, no differential signal is received by speaker 23, thus, no audiblenoise can be heard from speaker 23.

In one embodiment, this second time interval is approximately four tofive (4-5) micro-seconds. Subsequently, control 47 changes the state ofthe control signals to place circuit 25 in the third operating state.

FIG. 5 schematically illustrates system 10 during the third operatingstate. In FIG. 5, transistors 42, 43, 49, 55, 56, 64, and 65 areillustrated by switches that show the state (enabled or disabled) of therespective transistors responsively to the control signals of control47. Referring to FIG. 2 and FIG. 5, at a time T2 control 47 forces theC1 control signal high and the C2, C3, and C4 control signals low. Thelow C4 control signal disables transistor 42 and enables transistor 43which routes the voltage from node 37 around amplifier 40 throughresistor 41 to input 29. Thus, input 29 is maintained at the value ofthe voltage on node 37 and amplifier 40 may be disabled and to not driveinput 29. The low C4 signal also disables transistor 49 and decouplescapacitors 14 and 16 from input 29, thus, sources 11 and 12 can now forminput signals at respective inputs 33 and 34. The high C1 control signalmaintains the output of amplifiers 52 and 62 in the enabled state. Thelow C2 and C3 control signals disable transistors 55, 56, 64, and 65.With transistors 55 and 56 disabled, feedback resistor 57 is connectedas a gain resistor between the output and input of amplifier 50. Withtransistors 64 and 65 disabled, amplifier 60 receives differential inputsignals from inputs 33 and 34 and drives output 32. Amplifier 50receives the output of amplifier 60 through the gain of resistors 57 and66 and receives the reference voltage from input 29 and responsivelydrives output 31. In this configuration, the gain of any differentialinput signal received from sources 11 and 12 to the differential outputsignal between outputs 31 and 32 is shown by the equation below:

V31−V32=2(V11−V12)((R18)/(R15))

where;

-   -   V11=the voltage from source 11;    -   V12=the voltage from source 12; and    -   R15=the resistance of R15.

In order to facilitate this functionality for circuit 25, input 29 iscommonly connected to a first terminal of resistor 41, a source oftransistor 42, a drain of transistor 49, and a non-inverting input ofamplifier 51. A second terminal of resistor 41 is commonly connected toan inverting input of amplifier 40, an output of amplifier 40, a drainof transistor 42, and a source of transistor 43. A drain of transistor43 is commonly connected to a non-inverting input of amplifier 40, node37, a first terminal of resistor 38, and a first terminal of resistor36. A second terminal of resistor 38 is connected to return 27 and asecond terminal of resistor 36 is connected to input 26. A gate oftransistor 43 is connected to an output of inverter 44. An input ofinverter 44 is connected to a gate of transistor 42, a gate oftransistor 49, and the C4 output of control 47. A source of transistor49 is connected to input 33 and to a non-inverting input of amplifier61. An inverting input of amplifier 61 commonly connected to input 34, asource of transistor 64, and a source of transistor 65. An output ofamplifier 61 is connected to a drain of transistor 64, and to anon-inverting input of amplifier 62. An output of amplifier 62 isconnected to a drain of transistor 65, to output 32, and to a firstterminal of resistor 66. A second terminal of resistor 66 is commonlyconnected to a first terminal of resistor 57, a source of transistor 56,a source of transistor 55, and an inverting input of amplifier 51. Anoutput of amplifier 51 is connected to a drain of transistor 55 and to anon-inverting input of amplifier 52. An output of amplifier 52 iscommonly connected to output 31, a second terminal of resistor 57, and asource of transistor 56. A gate of transistor 56 is commonly connectedto a gate of transistor 65 and the C2 output of control 47. A gate oftransistor 55 is commonly connected to the gate of transistor 64 and theC3 output of control 47. The C1 output of control 47 is commonlyconnected to the enable input of amplifier 52 and the enable input ofamplifier 62. An input of control 47 is connected to input 30.

Those skilled in the art will appreciate that during the first operatingstate illustrated in FIG. 3, the outputs of amplifiers 50 and 60 aredisabled so that amplifiers 50 and 60 are not connected in aconfiguration that has any gain or gain control elements. During thisoperating state, the outputs of amplifiers 51 and 61 are clamped to thereference voltages used for respective subsequent stages 52 and 62,thus, the outputs of amplifiers 51 and 61 do not follow the voltage frombuffer 35.

FIG. 6 schematically illustrates a portion of an embodiment of amulti-stage amplifier 150 and a multi-stage amplifier 160 that arealternate embodiments of respective amplifiers 50 and 60 that areillustrated in FIG. 1. Amplifier 150 illustrates various otheramplification stages that may be positioned in series between amplifiers51 and 52. Transistor 55 is illustrated in FIG. 6 as being coupled tothe output of a second amplification stage after amplifier 51. However,transistor 55 maybe connected to the output of any amplifier stage thatis positioned between the output of amplifier 51 and the input ofamplifier 52. Amplifier 160 similarly illustrates various otheramplification stages that may be positioned in series between amplifiers61 and 62.

FIG. 7 schematically illustrates a portion of an embodiment of amulti-stage amplifier 155 and a multi-stage amplifier 165 that arealternate embodiments of respective amplifiers 50 and 60 that areillustrated in FIG. 1 and of respective amplifiers 150 and 160 that areillustrated in FIG. 6. Amplifier 155 is similar to amplifier 150 howeveramplifier 155 has an additional amplification stage of an amplifier 156that is inserted between the output of one of the series connectedamplifiers and transistor 55. Amplifier 156 provides buffering betweenthe output of the series connected amplifiers and transistor 55.Similarly, amplifier 165 includes an amplifier 166 that is positionedand that functions similarly to amplifier 156.

FIG. 8 schematically illustrates an embodiment of a portion of asingle-ended amplifier system 90 that uses amplifier circuit 25 in asingle-ended configuration to amplify single-ended signals. Amplifiercircuit 25 functions the same as described for differential amplifiersystem 10 of FIG. 1.

In this configuration, the gain of any differential signal received fromsources 11 and 12 to the differential output signal between outputs 31and 32 is shown by the equation below:

V31−V32=2(V11−V12)((R18)/(R15))

where;

-   -   R15=the resistance of R15.

FIG. 9 schematically illustrates an embodiment of a portion of anamplifier system 170 which includes an exemplary embodiment of anotheramplifier circuit 171 that uses a time-based algorithm to charge bypasscapacitor 20. Amplifier circuit 171 includes a first amplifier 174, asecond amplifier 176, and a clock control circuit or control 180.Control 180 is an alternate embodiment of control 47 of FIG. 1. Control180 is similar to control 47 except that control 180 may be configuredto form fewer operating states than control 47. Amplifiers 174 and 176generally are formed as differential amplifiers, such as operationalamplifiers that include feedback and gain resistors such as feedbackresistors 172 and 177 and gain resistors 175, 178 and 200. A switch,such as a transistor 173, is connected across resistor 172 to assist incharging capacitor 16. For the exemplary embodiment illustrated in FIG.9, control signal C1 is used to control transistor 173 and controlsignal C4 is used to control transistor 49. During the first operatingstate, control 180 asserts the C1 and C4 signals. Signal C1 enablestransistor 173 and signal C4 enables transistor 49 so that capacitors14, 16, and 20 may be charged to the reference voltage formed byresistors 36 and 38. Bypass buffer 35 (FIG. 1) may also be used tocharge capacitors 14, 16, and 20 at a faster rate. The time interval ofthe first operating state is chosen to be long enough to ensure thatcapacitors 14, 16, and 20 become charged to the desired value of thevoltage formed by resistors 36 and 38. After the first time intervalexpires, control 47 negates the C1 and C4 control signals so thatamplifiers 174 and 176 may drive outputs 31 and 32 with the amplifiedsignal received from capacitors 14 and 16. In another embodiment, system170 may be coupled in a single ended configuration by omitting capacitor14, resistors 19 and 200, and signal 11 in addition to connecting input33 to input 29 as illustrated by a dashed line.

FIG. 10 schematically illustrates an enlarged plan view of a portion ofan embodiment of a semiconductor device or integrated circuit 100 thatis formed on a semiconductor die 101. Circuits 25 is formed on die 101.Die 101 may also include other circuits that are not shown in FIG. 8 forsimplicity of the drawing. Circuit 25 and device or integrated circuit100 are formed on die 101 by semiconductor manufacturing techniques thatare well known to those skilled in the art.

In view of all of the above, it is evident that a novel device andmethod is disclosed. Included, among other features, is configuring anamplifier circuit to disable an output stage of an amplifier while anintermediate gain stage of the amplifier circuit is used to reduce noiseon the output of the amplifier circuit, and particularly while chargingreference and input capacitances of the amplifier circuit. Also includedis configuring the amplifier circuit to form a plurality of operatingstates that are also used to stabilize the elements.

While the subject matter of the invention is described with specificpreferred embodiments, it is evident that many alternatives andvariations will be apparent to those skilled in the semiconductor arts.Additionally, the word “connected” is used throughout for clarity of thedescription, however, it is intended to have the same meaning as theword “coupled”. Accordingly, “connected” should be interpreted asincluding either a direct connection or an indirect connection.

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 19. A method of forming anamplifier circuit comprising: forming a first amplifier having a firstinput, a second input, and having an output coupled to a first output ofthe amplifier circuit; forming a second amplifier having a first input,a second input, and having an output coupled to a second output of theamplifier circuit; configuring the amplifier circuit to have an inputcoupled to a capacitor external to the amplifier circuit; andconfiguring the amplifier circuit to form a first time interval andselectively couple the amplifier circuit to charge the capacitor duringthe first time interval, and to subsequently form a second timeinterval, and selectively decouple the amplifier circuit from chargingthe capacitor and to also couple the amplifier circuit to amplify aninput signal.
 20. The method of claim 19 wherein configuring theamplifier circuit to form a first time interval includes configuring adigital control circuit to digitally form the first time interval as asubstantially fixed time interval; configuring the digital controlcircuit to form a third time interval subsequent to the first timeinterval and before forming the second time interval; and configuringthe amplifier circuit to stop charging the capacitor responsively to thethird time interval and to selectively amplify the input signalresponsively to the second time interval.